(1) Field of the Invention
The present invention relates to a data control device and an ATM (Asynchronous Transfer Mode) control device, and more particularly, to a data control device for controlling operations on data and an ATM control device for controlling ATM communications.
(2) Description of the Related Art
Conventionally, a data communication system includes a processor (CPU) for performing operations and a memory (or registers) for storing data. The processor controls access to the memory and executes operations.
As a technique of performing such operations, pipeline processing in which a plurality of instructions are processed in an overlapped fashion is widely used to improve the throughput of the system.
FIG. 11 illustrates a flow of operations by means of a conventional pipeline, wherein the relationship between the occurrences of events and operations performed by the processor is indicated in time sequence of pipelining.
[S10] Following the occurrence of an event A, attribute analysis (analysis of data access range, etc.) of data related to the event A is carried out.
[S11] In response to the occurrence of an event B, the attribute analysis of data related to the event B is performed. Further, the data related to the event A is read from memory.
[S12] In response to the occurrence of an event C, the attribute analysis of data related to the event C is carried out. Also, the data related to the event B is read from memory. Further, operation on the data related to the event A is performed.
[S13] The data related to the event C is read from memory, and also operation on the data related to the event B is performed. Further, the data related to the event A is written in memory.
Subsequently, processes are performed in the order illustrated in the figure. Pipeline processing like this makes it possible to improve the apparent efficiency of processing instructions.
With the above conventional pipeline processing, however, the processor needs to analyze the attribute of data before performing a series of processes including memory read, operation, and memory write. Consequently, the data access time correspondingly increases, lowering the efficiency.
Also, in the conventional pipeline processing, if different instructions simultaneously require read access and write access, respectively, to an identical address of the memory (e.g. if in Step S13, the memory read responsive to the event C and the memory write responsive to the event A require access to the same address), then a pipeline hazard occurs, giving rise to a problem that the pipeline temporarily stops.
On the other hand, where the required logic for controlling the execution of instructions, like the one mentioned above, is implemented by a hard-wired configuration using a linear sequential circuit, instead of a processor, with a view to attaining high-speed processing, the hardware needs to be redesigned when even a slight change is made to the standard or to the design specification and thus lacks flexibility.